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Ordering number: EN
5632
LC86E5032
CMOS LSI
LC86E5032 8-Bit Single-Chip Microcontroller Preliminary Overview
The LC86E5032 microcontroller, a new addition to the LC865000 series, is an 8-bit single chip CMOS microcontroller with UVEPROM. This microcontroller has the same functions and pin assignment as for the LC865000 series mask ROM version, and a 32Kbyte EPROM. Program data is rewritable. It is suitable for program developments.
Package Dimensions
unit : mm
3126-DIC64S
[LC86E5032]
58.0
64
33
1
32
5.8max
1.27
3.4min
0.9
0.46
1.778
SANYO : DIC64S
3194-QFC64E
[LC86E5032]
20.0 4.7max 3.0 1.0 2.22 4.2
Features
3.0
13.97 1.0
48 49
1.0
33 32
(1) Option switching using EPROM data The optional functions of the LC865000 series can be specified using EPROM data. The trial products of the LC86E5032 can be evaluated with the mass production board. (2) Internal EPROM capacity : 32768 bytes (3) Internal RAM capacity : 512 bytes
Mask ROM version LC865032 LC865028 LC865024 LC865020 LC865016 LC865012 LC865008 PROM capacity 32512 bytes 28672 bytes 24576 bytes 20480 bytes 16384 bytes 12288 bytes 8192 bytes
13.97
20.0
1.0
64 1
0.8
17 16
0.35 0.15
0.35
0.8
SANYO : QFC64E
RAM capacity 512 bytes 512 bytes 512 bytes 384 bytes 384 bytes 384 bytes 384 bytes
(4) (5) (6) (7) (8) (9)
Operating voltage : 4.5 to 6.0 V Instruction cycle time : 0.98 to 400 s Operating temperature range : +10C to +40C The pin compatible with the mask ROM version Applicable mask version : LC865032, LC865028, LC865024, LC865020, LC865016, LC865012, LC865008 Factory shipment : DIC-64S QFC-64E
SANYO Electric Co., Ltd. Semiconductor LSI Div. Microcomputer Development Dep. O3197HA (II) No. 5632-1/21
0.25
19.05
18.8
LC86E5032
Usage Notes
When using, please take note of the following.
(1) Differences between the LC86E5032 and the LC865000 series
Items Port status at reset Operation after releasing reset LC86E5032 Please refer to "Port status at reset" on the next page. The option is specified by degrees within 3 ms after applying a 'H' level to the reset pin. The program is located at 00H is executed. 4.5 to 6.0 V +10C to +40C The program located at 00H is executed immediately after applying a 'H' level the reset pin. 2.7 to 6.0 V -30C to +70C LC865032/28/24/20/16/12/08
Operating voltage range (VDD ) Operating temperature range (Topr) Total output current [ IOAH (1) ] [ IOAH (1) ] Current drain [ IDDOP(1)] [ IDDOP(2)] [ IDDOP(3)] [ IDDOP(4)]
Refer to 'Electrical Characteristics' on the semiconductor news.
* LC86E5032 Options.
Options Configuration of input/output ports Pins, Circuits Port 0 (Can be specified for each bit.) Ports 1, 2 (Can be specified for each bit.) Ports 3, 4, 5 (Can be specified for each bit.) Port 7 pull-up MOS transistor Port 7 (Can be specified for each bit.) 1. Input Output 2. Input Output 1. Input Output 2. Input Output 1. Input Output 2. Input Output Option settings : No pull-up MOS transistor : N-channel open drain : Pull-up MOS transistor : CMOS : No programmable pull-up MOS transistor : N-channel open drain : Programmable pull-up MOS transistor : CMOS : No programmable pull-up MOS transistor : N-channel open drain : Programmable pull-up MOS transistor : CMOS
1. Pull-up MOS transistor not provided 2. Pull-up MOS transistor provided *P74 has no pull-up resistor option.
At reset, some port operations related to the option are different between the LC86E5032 and the LC865032/28/24/20/16/12/08. Please refer to the next table.
No. 5632-2/21
LC86E5032
* Port configuration at reset
Pin P0 Option settings Input : No pull-up MOS transistor Output : N-channel open drain Input : Pull-up MOS transistor Output : CMOS LC86E5032 (Same as for the mask version) Input mode * The pull-up MOS transistor is not present during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS transistor is present. (Output is OFF) (Same as for the mask version) LC865032/28/24/20/16/12/08 Input mode without pull-up MOS transistor (Output is OFF) Input mode with pull-up MOS transistor (Output is OFF)
P1, P2
Input : Programmable pull-up MOS transistor Output : N-channel open drain
Input mode without pull-up MOS transistor (Output is OFF) Input mode without pull-up MOS transistor (Output is OFF) Input mode without pull-up MOS transistor (Output is OFF) Input mode without pull-up MOS transistor (Output is OFF) Input mode without pull-up MOS transistor Input mode with pull-up MOS transistor
Input : Programmable pull-up MOS transistor (Same as for the mask version) Output : CMOS P3, P4, P5 Input : Nonprogrammable pull-up MOS transistor Output : N-channel open drain Input : Programmable pull-up MOS transistor Output : CMOS P7 Pull-up MOS transistor not provided Pull-up MOS transistor provided (Same as for the mask version)
(Same as for the mask version)
(Same as the mask version) Input mode * The pull-up MOS transistor is not present during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS transistor is present.
(2) Option The LC86E5032 uses 256 bytes addressed 7F00H to 7FFFH in program memory as option data area. This area does not affect the execution of program but means that the LC865032 program memory is 32512 bytes addressed 0000H to 7EFFH. The option data is specified by the option-setting program "SU865000. EXE". The specified option data is linked to the program area by linkage editor "L865000. EXE". (3) ROM space 7FFFH 7F00H 7EFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH 32K 0FFFH LC865032 LC865028 LC865024 LC865020 LC865016 LC865012 LC865008 28K 24K 20K 16K 12K 8K Option data area 256 bytes Option Data Area Option Data Area Option Data Area Option Data Area Option Data Area Option Data Area
No. 5632-3/21
LC86E5032
Writing to EPROM
(1) Specification of options Programming data for the LC86E5032's EPROM is required. The debugged evaluation file (EVA file) must be converted to an INTEL-HEX format file (HEX file) with the file converter program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86E5032. (2) How to write data to EPROM The LC86E5032 can be programmed by a general-purpose EPROM programmer with attachments W86EP5032D and W86EP5032Q. * Recommended EPROM programmers
Supplier Advantest Andou AVAL Minato Electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL 1890A
* "27512 (Vp-p = 12.5 V) Intel high-speed programming" mode should be used. The address must be set to "0000H to 7FFFH" and the jumper (DASEC) must be set 'OFF' at programming. (3) How to use the data security function "Data security" is a function to prevent the EPROM data from being read. Instructions on using the data security function: 1. Set the jumper of the attachment 'ON'. 2. Attempt to program the EPROM. The EPROM programmer displays an error. The error is a result of normal activity of the data security feature. This is not a problem with the EPROM programmer chip. Notes * The data security function is not carried out when the data of all address contain 'FF' at step 2 above. * Data security cannot be executed when the sequential writing operation of programming "BLANK=>PROGRAM=>VERIFY" is used at step 2 above. * Set the jumper 'OFF' after the execution of data security. (4) Erasing data Use a general-purpose EPROM eraser to erase the written data. (5) Shielding The UVEPROM (ultraviolet erasable programmable ROM) is incorporated in the IC. Cover the window of the IC with a seal in use. Data security Pin 1 mark
O F
OFF
ON
OFF
F
ON
ON
OF F
ON
Pin 1
Data security OFF
Pin 1
Data security OFF W86EP5032Q
W86EP5032D
No. 5632-4/21
LC86E5032
Pin Assignment
P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB11 P15/SCK1 P16/BUZ P17/PWM TEST1 RES XT1/p74 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P70/INT0 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN P30 P31 P32 P33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P07 P06 P05 P04 P03 P02 P01 P00 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VSS P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 SANYO : DIC64S Top view
No. 5632-5/21
LC86E5032
Pin Assignment
P14/SI1/SB1
P11/SI0/SB0
P15/SCK1
P12/SCK0
P17/PWM
P16/BUZ
P13/SO1
P10/SO0
P07
P06
P05
P04
P03
P02
P01
48
P00
32
47
46
45
44
43
42
41
40
39
38
37
36
35
34
TEST1 RES XT1/P74 XT2 V SS CF1 CF2 V DD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 64
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
33
P27 P26 P25 P24 P23 P22 P21 P20 V DD V PP V SS P51 P50 P47 P46 P45 P44
31 30 29 28 27 26 25 24 23 22 21 20 19 18
10
11
12
13
14
15 P42
1
3
5
2
4
6
7
8
9
17
P31
P33
P36
P30
P32
P34
P35
P37
P40
P70/INT0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
P41
P43
16
Top view SANYO : QFC64E
No. 5632-6/21
LC86E5032
System Block Diagram
Interrupt control
IR
PLA A16 to A0 D7 to D0 TA CE OE DASEC VDD VPP
Standby control
EPROM control
CF RC X tal ACC
Colck generator
EPROM(32KB)
PC
Base timer
Bus interface
B register
SIO 0
Port 1
C register
SIO 1
Port 7
ALU
Timer 0
Port 8
Timer 1
Port 2
PSW
ADC INT0 to INT3 Noise rejection filter Real-time service XRAM 128 bytes
Port 3
RAR
Port 4
RAM
Port 5
Stack pointer
Port 0
Watchdog timer
No. 5632-7/21
LC86E5032
LC86E5032 Pin Description
Pin name VSS VDD VDDVPP PORT0 P00 to P07 I/O I/O Function description Power supply pin (-) Power supply pin (+) Power supply pin (+) * 8-bit input/output port * Input for port 0 interrupt * Input/output in nibble units * Input for HOLD release * 8-bit input/output port * Data direction can be specified for each bit. * Other pin functions P10 : SIO0 data output P11 : SIO0 data input/bus input/output P12 : SIO0 clock input/output P13 : SIO1 data output P14 : SIO1 data input/ bus input/output P15 : SIO1 clock input/output P16 : Buzzer output P17 : Timer 1 output (PWM output) * 8-bit input/output port * Data direction can be specified for each bit. * 8-bit input/output port * Data direction can be specified for each bit. * 15 V withstand at N-ch open-drain output * 8-bit input/output port * Data direction can be specified for each bit. * 15 V withstand at N-ch open-drain output * 2-bit input/output port. * Data direction can be specified for each bit. * 15 V withstand at N-ch open-drain output * 5-bit input port * Other pin functions P70 : INT0 input/HOLD release/N-channel transistor output for watchdog timer. P71 : INT 1 input/HOLD release. P72 : INT 2 input/timer 0 event input. P73 : INT 3 input with noise filter/timer 0 event input. P74 : Input pin XT1 for 32.768 kHz crystal oscillation * Interrupt received format, vector address. Rising Falling Rising & falling Disable Disable Enable Enable High level Enable Enable Disable Disable * Pull-up resistor : Present/Not present * Output form : CMOS/ N-channel open-drain. Output form : CMOS/ N-channel open-drain Data input/output * D0 to D7 Power for programming Option Function in PROM mode
PORT1 P10 to P17
I/O
PORT2 P20 to P27 PORT3 P30 to P37 PORT4 P40 to P47 PORT5 P50 to P51 PORT7 P70 P71 to P74
I/O I/O
Output form : CMOS/ N-channel open-drain Output form : CMOS/ N-channel open-drain Output form : CMOS/ N-channel open-drain Output form : CMOS/ N-channel open-drain Pull-up resistor : Present/Not present (P70, 71, 72, 73) * P74 has no pull-up resistor. Address input * A7 to A0 Address input * A14 to A8 (*5) * P47 : TA (*4)
I/O
I/O
I/O I
Input of PROM control signal * DASEC (*1) * OE (*2) * CE (*3)
Low level Enable Enable Disable Disable
Vector
INT0 INT1 INT2 INT3
Enable Enable Enable Enable
Enable Enable Enable Enable
03H 0BH 13H 1BH
No. 5632-8/21
LC86E5032
Pin name PORT8 P80 to P87 RES TEST1 XT1/P74 I/O I Function description * 8-bit input port * Other functions AD input port (8 port pins) Reset pin Test pin Should be left open. * Input pin for 32.768 kHz crystal oscillation * Other function : Input port P74 When not used, connect to VDD. Output pin for 32.768 kHz crystal oscillation When not used, should be left open. Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation Option Function in PROM mode
I O I
XT2 CF1 CF2
O I O
* All port options can be specified in bit units. *1 *2 *3 *4 *5 Memory select input for data security Output enable input Chip enable input TA PROM control signal input A14 Address input
* Connect as shown in the following figure to reduce noise into VDD pin. Short-circuit the VDD pin to the VDDVPP pin. Short-circuit the VSS pin to the VSS pin.
LSI VDD
Power supply
VDDVPP VSS VSS
No. 5632-9/21
LC86E5032
1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol Pins Conditions VDD[V] Supply voltage Input voltage VDD max VI(1) VDD,VDDVPP * Ports 71, 72, 73, 74 * Port 8 * RES * Ports 0, 1, 2 * Ports 3, 4, 5 of CMOS output * Ports 3, 4, 5 of opendrain output Ports 0, 1, 2, 3, 4, 5 * CMOS output * At each pin Total of all pins Total of all pins At each pin At each pin Total of all pins Total of all pins Total of all pins Ta = +10C to +40C Ta = +10C to +40C 10 -65 VDD = VDDVPP min -0.3 -0.3 Ratings typ max +7.0 VDD+0.3 V Unit
Input/output voltage
VIO(1)
-0.3
VDD+0.3
VIO(2) Highlevel output current Peak output current Total output current Peak output current Total output current Power dissipation (max.) Operating temperature range Storage temperature range IOPH(1)
-0.3 -4
+15 mA
IOAH(1) IOAH(2) IOPL(1) IOPL(2) IOAL(1) IOAL(2) IOAL(3) Pd max(1) Pd max(2) Topr Tstg
Ports 0, 1, 2 Ports 3, 4, 5 Ports 0, 1, 2, 3, 4, 5 Port 70 Ports 0, 1, 70 Port 2 Ports 3, 4, 5 DIC64S QFC64E
-25 -20 20 15 40 40 80 720 420 40 +150 C mW
Lowlevel output current
No. 5632-10/21
LC86E5032
2. Recommended Operating Range at Ta = +10C to +40C, VSS = 0 V
Parameter Symbol Pins Conditions VDD[V] Operating voltage range HOLD voltage VDD(1) VHD VDD VDD 0.98 s tCYC tCYC 400 s RAM and registers retain their pre-HOLD mode values. (Schmitt) Output disabled Output disabled 4.5 to 6.0 min 4.5 2.0 Ratings typ max 6.0 6.0 V Unit
Input high voltage
VIH(1) VIH(2)
Port 0
0.4VDD +0.9
VDD VDD
* Ports 1, 2 * Ports 72, 73 (Schmitt) * Port 70 Port input/interrupt. * Port 71 * RES (Schmitt) Port 70 Watchdog timer * Port 74 * Port 8 Ports 3, 4, 5 of CMOS output (Schmitt) Ports 3, 4, 5 of open drain output (Schmitt) Port 0 (Schmitt)
4.5 to 6.0 0.75VDD
VIH(3)
Output N-channel transistor OFF
4.5 to 6.0 0.75VDD
VDD
VIH(4) VIH(5) VIH(6)
Output N-channel transistor OFF Output N-channel transistor OFF Output disabled
4.5 to 6.0
0.9VDD
VDD VDD VDD
4.5 to 6.0 0.75VDD 4.5 to 6.0 0.75VDD
VIH(7)
Output disabled
4.5 to 6.0 0.75VDD
13.5
Input low voltage
VIL(1) VIL(2)
Output disabled Output disabled
4.5 to 6.0 4.5 to 6.0
VSS VSS
0.2VDD 0.25VDD
* Ports 1, 2, 3, 4, 5 * Ports 72, 73 (Schmitt) * Port 70 Port input/interrupt. * Port 71 * RES (Schmitt) Port 70 Watchdog timer * Port 74 * Port 8
VIL(3)
N-channel transistor OFF
4.5 to 6.0
VSS
0.25VDD
VIL(4) VIL(5) Operation cycle time tCYC
N-channel transistor OFF N-channel transistor OFF
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
VSS VSS 0.98
0.8VDD -1.0 0.25VDD 400 s
No. 5632-11/21
LC86E5032
Parameter Symbol Pins Conditions VDD[V] Oscillation frequency range (Note 1) FmCF(1) CF1, CF2 * 12 MHz (ceramic resonator oscillation). * Refer to Figure 1. * 3 MHz (ceramic resonator oscillation). * Refer to Figure 1. RC oscillation XT1, XT2 * 32.768 kHz (crystal oscillation). * Refer to Figure 2. * 12 MHz (ceramic resonator oscillation). * Refer to Figure 3. * 3 MHz (ceramic resonator oscillation). * Refer to Figure 3. * 32.768 kHz (crystal oscillation). * Refer to Figure 3. 4.5 to 6.0 min 11.76 Ratings typ 12 max 12.24 MHz Unit
FmCF(2)
CF1, CF2
4.5 to 6.0
2.94
3
3.06
FmRC FsXtal
4.5 to 6.0 4.5 to 6.0
0.4
0.8 32.768
2.0 kHz
Oscillation stable time period (Note 1)
tmsCF(1)
CF1, CF2
4.5 to 6.0
0.03
0.5
ms
tmsCF(2)
CF1, CF2
4.5 to 6.0
0.2
2
tssXtal
XT1, XT2
4.5 to 6.0
1
1.5
s
(Note 1) Refer to Table 1 and Table 2 for the oscillation constants.
No. 5632-12/21
LC86E5032
3. Electrical Characteristics at Ta= +10C to +40C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Input high current IIH(1) * Ports 3, 4, 5 at open-drain output 4.5 to 6.0 * Output disabled * VIN = 13.5 V (including off-state leak current of output transistor) * Output disabled 4.5 to 6.0 * Pull-up MOS transistor OFF. VIN = V DD (including off-state leak current of output transistor) 4.5 to 6.0 min Ratings typ max 5 A Unit
IIH (2)
* Port 0 without pull-up MOS transistor * Ports 1, 2, 3, 4, 5
1
IIH (3)
* Ports 70, 71, 72, 73 VIN= VDD without pull-up MOS transistor * Port 8 * RES * Ports 1, 2, 3, 4, 5 * Port 0 without pull-up MOS transistor VIN = V DD
1
IIH (4) Input low current IIL(1)
4.5 to 6.0 -1
1
* Output disabled 4.5 to 6.0 * Pull-up MOS transistor OFF. VIN = V SS (including off-state leak current of output transistor) 4.5 to 6.0
I IL(2)
* Ports 70, 71, 72, 73 VIN = V SS without pull-up MOS transistor * Port 8 * RES VIN = V SS
-1
I IL(3) Output high voltage VOH (1) VOH (2) Output low voltage VOL (1) VOL (2) VOL (3) VOL (4) Pull-up MOS transistor resistance Hysteresis voltage Pin capacitance Rpu VHIS
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
-1 VDD-1 VDD-0.5 1.5 0.4 0.4 0.4 15 40 0.1VDD 70 k V V
* Ports 0, 1, 2, 3, 4, 5 I OH = -1.0 mA at CMOS output I OH = -0.1 mA Ports 0, 1, 2, 3, 4, 5 I OL = 10 mA IOL = 1.6 mA Port 70 I OL = 1 mA I OL = 0.5 mA * Ports 0, 1, 2, 3, 4, 5 VOH = 0.9 VDD * Ports 70, 71, 72, 73 * Ports 0, 1, 2, 3, 4, 5 Output disable * Ports 70, 71, 72, 73 * RES All pins * f = 1 MHz * Unmeasured input pins are set to VSS level. * Ta = 25C
CP
4.5 to 6.0
10
pF
No. 5632-13/21
LC86E5032
4. Serial Input/Output Characteristics at Ta = +10C to +40C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Cycle Lowlevel pulse width Highlevel pulse width Cycle tCKCY(1) tCKL(1) SCK0, SCK1 Refer to Figure 5. 4.5 to 6.0 4.5 to 6.0 min 2 1 Ratings typ max tCYC Unit
Input clock
tCKH(1)
4.5 to 6.0
1
Serial clock
tCKCY(2)
SCK0, SCK1
Output clock
Lowlevel pulse width Highlevel pulse width
tCKL(2)
* Use pull-up resistor (1 k) when set to open-drain output. * Refer to Figure 5.
4.5 to 6.0
2
4.5 to 6.0
1/2tCKCY
tCKH(2)
4.5 to 6.0
1/2tCKCY
Serial input
Data setup time Data hold time Output delay time (Serial clock is extrnal clock.) Output delay time (Serial clock is internal clock.)
tICK tCKI
* SI0, SI1 * SB0, SB1
* Data set-up to SCK0, 1 * Data hold from SCK0, 1 * Refer to Figure 5.
4.5 to 6.0 4.5 to 6.0
0.1 0.1
s
tCKO(1)
* SO0, SO1 * SB0, SB1
* Use pull-up resistor (1 k) when set to open-drain output.
4.5 to 6.0
7/12tCYC +0.2
Serial output
tCKO(2)
* Data hold from SCK0, 1 * Refer to Figure 5.
4.5 to 6.0
1/3tCYC +0.2
No. 5632-14/21
LC86E5032
5. Pulse Input Conditions at Ta = +10C to +40C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] High/low-level pulse width tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIL(4) * INT0, INT1 * INT2/T0IN * INT3 INT3 (The noise rejection clock selected to 1/1.) * Interrupt acceptable * Timer 0 pulse countable * Interrupt acceptable * Timer 0 pulse countable 4.5 to 6.0 min 1 Ratings typ max tCYC Unit
4.5 to 6.0
2
* Interrupt acceptable INT3 * Timer 0 pulse (The noise rejection clock selected to 1/16.) countable RES Reset acceptable
4.5 to 6.0
32
4.5 to 6.0
200
s
6.
A/D Converter Characteristics at Ta = +10C to +40C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] min Ratings typ 8 1/5 15.68 (tCYC = 0.98 s) 31.36 (tCYC = 0.98 s) 4.5 to 5.5 VAIN = V DD VAIN = V SS 4.5 to 5.5 4.5 to 5.5 -1 VSS 65.28 (tCYC = 4.08 s) 130.56 (tCYC = 4.08 s) VDD +1 V A max bit LSB s Unit
Resolution Absolute precision (Note 2) Conversion time
N ET tCAD A/D conversion time = 16 x tCYC (ADCR2 = 0) (Note 3) A/D conversion time = 32 x tCYC (ADCR2 = 1) (Note 3)
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
Analog input voltage range Analog port input current
VAIN I AINH I AINL
AN0 to AN7
(Note 2) Absolute precision excepts quantizing error (1/2 LSB). (Note 3) The conversion time is the time from execution of the instruction to start conversion to the completion of shifting the A/D converted value to the register.
No. 5632-15/21
LC86E5032
7. Current Drain Characteristics at Ta = +10C to +40C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Current drain during basic operation (Note 4) I DDOP(1) VDD * FmCF = 12 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : CF oscillator. * Internal RC oscillator stopped. * FmCF = 3 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : CF oscillator. * Internal RC oscillator stopped. * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : RC oscillator. * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : crystal oscillator. * Internal RC oscillator stopped. 4.5 to 6.0 min Ratings typ 13 max 26 mA Unit
I DDOP(2)
4.5 to 6.0
7
14
I DDOP(3)
4.5 to 6.0
4
10
I DDOP(4)
4.5 to 6.0
4
8
No. 5632-16/21
LC86E5032
Parameter Symbol Pins Conditions VDD [V] Current drain at HALT mode (Note 4) IDDHALT(1) VDD * HALT mode * FmCF = 12 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : CF oscillator. * Internal RC oscillator stopped. * HALT mode * FmCF = 3 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : CF oscillator. * Internal RC oscillator stopped. * HALT mode * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : RC oscillator * HALT mode * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : crystal oscillator. * Internal RC oscillator stopped. VDD HOLD mode 4.5 to 6.0 min Ratings typ 5 max 10 mA Unit
IDDHALT(2)
4.5 to 6.0
2.2
4.6
IDDHALT(3)
4.5 to 6.0
550
1100
A
IDDHALT(4)
4.5 to 6.0
25
100
Current drain at HOLD mode (Note 4)
I DDHOLD(1)
4.5 to 6.0
0.05
30
I DDHOLD(2)
2.5 to 4.5
0.02
20
(Note 4) The currents of output transistors and pull-up transistors are ignored.
No. 5632-17/21
LC86E5032
Table 1. Ceramic Resonator Oscillation Guaranteed Constants (Main clock)
Oscillation type 12 MHz ceramic resonator oscillation Kyocera 3 MHz ceramic resonator oscillation Kyocera Murata Supplier Murata Oscillator CSA12.0MTZ CST12.0MTW KBR-12.0M CSA3.00MG040 CST3.00MGW040 KBR-3.0MS 47 pF 33 pF 100 pF C1 33 pF on chip 33 pF 100 pF on chip 47 pF C2 33 pF
* Both C1 and C2 must use K rank (10%) and SL characteristics. Table 2. Crystal Oscillation Guaranteed Constants (Sub-clock)
Oscillation type 32.768 kHz crystal oscillation Supplier Dai Sinku Kyocera Oscillator DT-38(1TA252E00) KF-38G-13P0200 C3 18 pF 18 pF C4 18 pF 18 pF
* Use J rank (5%) and CH characteristics for C3 and C4. (If high precision is unnecessary, use K rank (10%) and SL characteristics.)
Notes * Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest pattern length. * If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
C1
CF
C2
C3
X tal
C4
Figure 1
Main-clock circuit Ceramic Resonator Oscillation
Figure 2
Sub-clock circuit Crystal Oscillation
No. 5632-18/21
LC86E5032
VDD VDD lower limit 0V Reset time
Power supply
RES
Internal RC resonator oscillation CF1, CF2
tmsCF
tssXtal XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode

HOLD release signal
Valid
Internal RC resonator oscillation CF1, CF2
tmsCF
tssXtal XT1, XT2
Operation mode
HOLD
Instruction execution mode

Figure 3 Oscillation Stable Time
VDD VDD RRES RES CRES
The values of CRES and RRES should be determined (Note) Fix the at least of s, measured from such that reset time isvalue 200 CRES, RRES that is moment thereset untill the VDD lower limit. the sure to power exceeds 200s, after
Power supply has been over inferior limit of supply voltage.
Figure 4 Reset Circuit No. 5632-19/21
LC86E5032
0.5VDD 0.5V DD < AC timing point >
tCKCY tCKL
SCK0 SCK1
VDD VDD
tCKH 1k tICK tCKI
SI0 SI1
tCKO
SO0,SO1 SB0,SB1
50pF
< Timing >
< Test load >
Figure 5 Serial Input/Output Test Conditions
tPIL
tPIH
Figure 6 Pulse Input Timing Conditions
No. 5632-20/21
LC86E5032
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co. , Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 1997. Specifications and information herein are subject to change without notice.
No. 5632-21/21

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